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SMS66
Six-Channel Power Supply Supervisor and Cacsade Sequence Controller
FEATURES & APPLICATIONS
* * * * * * * * Very accurate monitor function - 5mV steps Monitors and sequences up to six supplies Programmable Power-on/-off sequencing Monitors internal temperature sensor Operates from 12V or 3.3V supply Monitors 12V input and VDD Monitors two general-purpose 10-bit ADC inputs Programmable threshold limits (2 OV/2 UV) for each monitored input * Programmable RESET, HEALTHY and FAULT functions * 4k-bit general purpose nonvolatile memory * I2C 2-wire serial bus for programming configuration and monitoring status, including 10-bit ADC conversion results Applications * Monitor and Sequence Distributed Power and Point of Load Power Supplies * Multi-voltage Processors, DSPs, ASICs used in Telecom, CompactPCI or server systems Preliminary Information1 (See Last Page)
INTRODUCTION
The SMS66 is a very accurate programmable power supply supervisor that monitors and sequences. It controls sequencing time and position of up to six isolated or non-isolated distributed or POL DC/DC converters. The monitor supervisory function has two independent UV and OV settings for each supply and can be set in 5mV steps. The SMS66 also sequences the power supplies in any order using enable outputs with programmable polarity. The SMS66 monitors six power supply channels as well as VDD, 12V input, two general-purpose analog inputs and an internal temperature sensor using a 10bit ADC. The 10-bit ADC can measure the value on any one of the input channels and output the conversion data via the I2C bus. Using the I2C interface, a host system can communicate with the SMS66 status register, optionally control Power-on/off, and utilize 4 K-bits of nonvolatile memory.
SIMPLIFIED APPLICATIONS DRAWING
12VIN (+8V to +15V Range) VDD (+2.7V to +5.5V Range) 12VIN VDD DC/DC Converter A VIN Vout 2.5VIN 12V 3.3V
SDA I2C BUS SCL A2 PUPA External or Internal TEMP SENSOR ON/OFF
AIN1
SMS66
VMA DC/DC Converter F VIN Vout
P/ DSP/ NPU/ FPGA
1.2VIN
External or Internal REFERENCE
VREF_OUT VREF_ADC HEALTHY PUPF ON/OFF
RST
MR
VMF HEALTHY RESET DONE
Figure 1 - Applications Schematic using the SMS66 Controller to cascade sequence up to six DC/DC Converters while also providing supervisory functions.
Note: This is an applications example only. Some pins, components and values are not shown. (c) SUMMIT Microelectronics, Inc. 2003 * 300 Orchard City Drive, #131 * Campbell CA 95006 * Phone 408 378-6461 * FAX 408 378-6596 2070 1.0 7/16/03
www.summitmicro.com
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SMS66
Preliminary Information
VDD (+2.7V to +5.5V) or 12VIN ( +8V to +15V) 2.7V 2.5V 2.0V 1.8V 1.5V
tDPONA
tDPONB RST# tDPONC
tDPOND
tDPONE
tDPONF tPRTO
Figure 2 - Example Power Supply Sequencing and System Start-up Initialization using the SMS66. Any order of supply sequencing can be applied using the SMS66 with very accurate monitoring and supervisory functions.
GENERAL DESCRIPTION
The SMS66 is a highly integrated power supply controller, monitor and sequencer. It has the ability to control, monitor and sequence up to six power supplies. Also, the SMS66 can monitor the VDD input, the 12V input, two general-purpose analog inputs and the internal temperature sensor. The SMS66 has three operating modes: Power-on sequencing mode, monitor mode, and Power-off sequencing mode. Power-on sequencing can be initiated via the PWR_ON/OFF pin or I2C control. In this mode, the SMS66 will sequence the power supply channels on in any order by activating the PUP outputs and monitoring the respective converter voltages to ensure cascading of the supplies. A programmable sequence termination timer can be set to disable all channels if the Power-on sequence stalls. During this mode the HEALTHY output will remain inactive and the RST output will remain active. Once the Power-on sequencing mode is complete, the SMS66 enters monitor mode. In the monitor mode the SMS66 supervises the supplies to within 5mV, and enables the triggering of outputs by monitored fault conditions. The 10-bit ADC cycles through all 11 channels every 2ms and checks the conversions against the programmed threshold limits. The results can be used to trigger RST, HEALTHY and FAULT outputs as well as to trigger a Power-off or a Force Shutdown operation. The Power-off sequencing mode can only be entered while the SMS66 is in the monitoring mode. It can be initiated by either bringing the PWR_ON/OFF pin inactive, through I2C control or triggered by a channel exceeding its programmed thresholds. Once Poweroff is initiated it will disable the Active DC Control and sequence the PUP outputs off in either the same or reverse order as Power-on sequencing and monitor the supply voltages to ensure cascading of the supplies as they turn off. The sequence termination timer can be programmed to immediately disable all channels if the Power-off sequencing stalls. The RST output will remain active throughout this mode while the HEALTHY output remains inactive.
Summit Microelectronics, Inc
2070 1.0 7/16/03
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SMS66
Preliminary Information
INTERNAL FUNCTIONAL BLOCK DIAGRAM
12VIN VDD VDD_CAP PWR_ON/OFF FS
VREF_ADC AIN1 AIN2 VM A CAPA
3.6V or 5.5V Regulator
Power Supply Arbitrator Sequence Control
PUPA PUPB PUPC PUPD PUPE PUPF
10-Bit ADC
Temperature Sensor
VM F MR CAPF RST HEALTHY FAULT
Output Control
VREF_OUT
Reference
Memory and Limit Registers
I2 C Interface
SDA SCL A2 GND
Figure 3 -SMS66 Internal Functional Block Diagram.
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SMS66
Preliminary Information
PIN DESCRIPTIONS
Pin Number 1 2 3 Pin Type DATA CLK IN Pin Name SDA SCL A2 I2C Bi-directional data line I2C Clock line The address pin is biased either to VDD_CAP or GND. When communicating with the SMS66 over the 2-wire bus A2 provides a mechanism for assigning a unique bus address. Programmable active high/low input. When asserted the RST output will be go active. When de-asserted the RST output will go inactive immediately after a reset timeout period (tPRTO) if there are no RST trigger sources active. This timeout period makes it suitable to use a pushbutton for manual reset. Programmable active high/low input signals the start of the power sequencing. When asserted the part will sequence the supplies on and when de-asserted the part will sequence the supplies off. Programmable active high/low input. Force shutdown is used to immediately turn off all converter enable signals (PUP outputs) Programmable active high/low open drain Fault output. Active when a programmed fault condition exists on AIN1, AIN2, or the internal temperature sensor. Programmable active high/low open drain Healthy output. Active when all programmed power supply inputs and monitored inputs are within OV and UV limits. Programmable active high/low open drain Reset output. Active when a programmed fault condition exists on any power supply inputs or monitored inputs or when MR is active. RST has a programmable timeout period with options for 0.64ms, 25ms, 100ms and 200ms. General purpose monitored analog input General purpose monitored analog input Ground Voltage reference input used for A/D conversion where: (4XVREF_ADC) = Full Scale for VMA-F and VDD (12XVREF_ADC) = FS for 12VIN (2XVREF_ADC) = FS for AIN1 and AIN2. VREF_ADC can be connected to VREF_CNTL in most applications. Voltage reference output for the internal 1.25V reference. Monitored voltage input, VMA through VMF Pin Description
4
IN
MR
5 6 7
IN IN OUT
PWR_ON/OFF FS FAULT
8
OUT
HEALTHY
9
OUT
RST
10 11 12, 44, 39, 34, 29, 24, 19
IN IN GND
AIN1 AIN2 GND
13
IN
VREF_ADC
14 41,36, 31,26, 21,16
O IN
VREF_OUT VMX
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SMS66
Preliminary Information
PIN DESCRIPTIONS (Cont.)
Pin Number 42,37, 32,27, 22,17 43,38, 33,28, 23,18 45, 40, 35, 30, 25, 20, 15 46 47 48 Pin Type CAP OUT Pin Name CAPX PUPX Pin Description External capacitor input used to filter the VMX inputs to the 10-bit ADC, CAPA through CAPF. This provides an RC filter where R = 25k. Programmable active high/low open drain converter enable output, PUPA through PUPF No Connection Power supply of the part 12V power supply input internally regulated to either 3.6V or 5.5V External capacitor input used to filter the internal supply
NC PWR PWR CAP
NC VDD 12VIN VDD_CAP
PACKAGE AND PIN CONFIGURATION
48 LEAD TQFP
VDD_CAP CAPA PUPB 38 12VIN CAPB 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 PUPA GND VDD VMA GND 39
48
47
46
45
NC
44
43
42
41
SDA SCL A2 MR PWR_ON/OFF FS FAULT HEALTHY RST AIN1 AIN2 GND
1 2 3 4 5 6 7 8 9 10 11 12
40
NC
VMB NC GND PUPC CAPC VMC NC GND PUPD CAPD VMD NC
VREF_ADC
VREF_OUT
VME
PUPF
CAPE
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2070 1.0 7/16/03
PUPE
CAPF
GND
VMF
GND
NC
NC
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SMS66
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ...................... -55C to 125C Storage Temperature............................ -65C to 150C Terminal Voltage with Respect to GND: VDD Supply Voltage ..........................-0.3V to 6.0V 12VIN Supply Voltage......................-0.3V to 15.0V All Others ................................-0.3V to VDD + 0.7V Output Short Circuit Current ............................... 100mA Lead Solder Temperature (10 secs) .................... 300C
Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended.
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Industrial)...........-40C to +85C (Commercial) ............-5C to +70C VDD Supply Voltage .................................. 2.7V to 5.5V EEPROM Write Supply Voltage1..............3.0V to 5.5V 12VIN Supply Voltage2 ............................ 8.0V to 15.0V VIN ............................................................ GND to VDD VOUT ...................................................... GND to 15.0V Package Thermal Resistance (JA) 48 Lead TQFP........................................80oC/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
Note 1 - During an EEPROM memory array or Configuration Register Write, the supply voltage minimum is 3.0V. Note 2 - Range depends on internal regulator set to 3.6V or 5.5V.
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max VDD Low Range Supply Voltage Note 1 Note 2. Internally regulated to 5.5V Note 2. Internally regulated to 3.6V 12VIN floating VDD floating 0 0 -0.005 -0.005 0 0 -0.005 -0.005
PTUV1 PTUV2
Unit V V
2.7 10 7 3 3
5.5 15 14 5 5 4XVREF 4XVREF PTUV PTOV +0.005 +0.005 4XVREF 4XVREF +0.005 +0.005
12VIN
High Range Supply Voltage Power Supply Current from VDD Power Supply Current from 12VIN Programmable Threshold for OV1 condition Programmable Threshold for OV2 condition Programmable UV Threshold Accuracy Programmable OV Threshold Accuracy Programmable Threshold for UV1 condition Programmable Threshold for UV2 condition Programmable UV1 Threshold Accuracy Programmable UV2 Threshold Accuracy
IDD I12VIN PTOV1 PTOV2 PTOV1ACC PTOV2ACC PTUV1 PTUV2 PTUV1ACC PTUV2ACC
mA mA V V V V V V V V
Note 1 - During an EEPROM memory array or Configuration Register Write, the supply voltage minimum is 3.0V. Note 2 - Range depends on internal regulator set to 3.6V or 5.5V. Summit Microelectronics, Inc 2070 1.0 7/16/03
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SMS66
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max PUP characteristics VOL Output Low Voltage ISINK = 2mA 0 0.4 All other input and output characteristics VDD = 2.7V 0.9xVDD VDD Input High Voltage VIH (FS,PWR_ON/OFF, MR#) VDD = 5.0V 0.7xVDD VDD VIL VOL IOL VMMonitor VAMonitor TMonitor VREF_OUT VREF TC VREF ACC External VREF Input Low Voltage (FS, PWR_ON/OFF, MR#) Programmable Open Drain Outputs (RST, HEALTHY, FAULT) Output Low Current VM Monitor Threshold Step Size AINx Monitor Threshold Step Size Temperature Threshold Step Size Internal 1.25VREF Output Voltage Internal VREF Temperature Coefficient Internal VREF Accuracy External VREF Voltage Range -40C to +85C -5C to +70C VDD = 2.7V VDD = 5.0V ISINK = 2mA
Note - Total ISINK from all PUPx pins should not exceed 3mA or accuracy specifications will be affected
Unit V V V V V V mA mV mV
o
-0.1 -0.1 0 0 5 2.5 0.25 1.24 -0.25 -0.15 -0.4 0.5 1.25
0.1xVDD 0.3xVDD 0.4 1.0
VM pins AIN1/AIN2 pins Internal Temp Sensor
C
1.26 +0.25 +0.15 +0.4
VDD_CAP
V % % % V
Summit Microelectronics, Inc
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SMS66
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max AIN1/AIN2 ADC characteristics N MC S/N DNL INL GAIN Offset ZSE FSE ADC_TC IMADC IIVREF_ADC ICVREF_ADC IRVREF_ADC Resolution Missing Codes Signal-to-Noise Ratio Differential Non-Linearity Integral Non-Linearity Positive full scale gain error Offset Error Zero Scale Error Full Scale Error Full Scale Temperature Coefficient Analog ADC Input Impedance VREF_ADC Input Current VREF_ADC Input Capacitance VREF_ADC Input Impedance AIN1, AIN2
Minimum resolution for which no missing codes are guaranteed
Unit
10 10 72 -1/2 -1 -0.5 -1 -1 -1 15 10 250 200 1 +1/2 +1 +0.5 +1 +1 +1
Bits Bits db LSB LSB % LSB LSB LSB PPM /oC M nA pF k
Conversion rate = 500Hz
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SMS66
Preliminary Information
AC OPERATING CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4B and 4C Timing diagrams.
Symbol tDPON
Description Programmable Power-on delay from VMX out-of-fault to PUPY active Programmable Power-off delay from VMX off to PUPY inactive Programmable Reset Time-Out Period Programmable Sequence Termination Timer 10-bit ADC sampling period
tDPOFF
tPRTO
tSTT tADC
Conditions 0.64ms 12.5ms 25ms 50ms 0.64ms 12.5ms 25ms 50ms 0.64ms 25ms 100ms 200ms 100ms 200ms 400ms Time for all 11 channels
Min -15
Typ tDPON
Max +15
Unit %
-15
tDPOFF
+15
%
-15
tPRTO
+15
%
-15
tSTT 2
+15
% ms
Summit Microelectronics, Inc
2070 1.0 7/16/03
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SMS66
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS - 100/400kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4A Timing Diagram.
Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR tWR
Description SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock Edge to Data Valid Data Output Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Filter SCL and SDA Write Cycle Time Write Cycle Time
Conditions Min 0 4.7 4.0
Before New Transmission - Note 1/
100kHz Typ Max 100 Min 0 1.3 0.6 1.3 0.6 0.6 0.6 3.5 0.2 0.2 1000 300 250 0 150 0 100 5 10
400kHz Typ Max 400 Units KHz s s s s s s 0.9 s s 1000 300 ns ns ns ns 100 5 10 ns ms ms
4.7 4.7 4.0 4.0
SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change
Note 1/ Note 1/
0.2 0.2
Noise suppression Memory Array Configuration Registers
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
tR SCL tSU:SDA SDA
(IN)
tF t HD:SDA
tHIGH
t W R (For W rite O peration Only) t LOW tSU:DAT tSU:STO tBUF
tHD:DAT
tAA SDA
(OUT)
t DH
Figure 4A . Basic I2C Serial Interface Timing
Summit Microelectronics, Inc
2070 1.0 7/16/03
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SMS66
Preliminary Information
TIMING DIAGRAMS (CONTINUED)
0 PUP A t DPONA 1 2
VM A
PUP B
t DPO NB
VM B t DPO NC PUP C
VM C
PUP D
t DPOND
VM D
Figure 4B - The SMS66 sequencing the supplies on and then monitoring for fault conditions.
2 PUP A 1 0
t DPOFFA
VM A
PUP B
t DPOFFB
VM B
PUP C t DPOFFC
VM C
PUP D
t DPOFFD
VM D
Figure 4C - The SMS66 sequencing the supplies off.
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SMS66
Preliminary Information
APPLICATIONS INFORMATION DEVICE OPERATION
POWER SUPPLY The SMS66 can be powered by either a 12V input through the 12VIN pin or by a 3.3V or 5.0V input through the VDD pin. The 12VIN pin feeds an internal programmable regulator that internally generates either 5.5V or 3.6V. A voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the VDD input. This voltage arbitration circuit continuously checks for these voltages to determine which will power the SMS66. The resultant internal power supply rail is connected to the VDD_CAP pin that allows both filtering and holdup of the internal power supply. MODES OF OPERATION The SMS66 has three basic modes of operation: Power-on sequencing mode, monitoring mode, and Power-off sequencing mode (shown in Figures 4B through 4E). In addition, there is a forced shutdown feature. A detailed description of each mode and feature follows. POWER-ON SEQUENCING The SMS66 can be programmed to sequence up to six power supplies in any order. Each of these six channels (A-F) has an associated open drain PUP output that, when connected to a converter's enable pin, controls the turn-on of the converter. The channels are assigned sequence positions to determine the order of the sequence. Any channel can also be programmed to not take part in the sequencing in applications with fewer than six supplies. The polarity of each of the PUPX outputs is programmable for use with various types of converters. Power-on sequencing can be initiated by the PWR_ON/OFF pin or via I2C control. The polarity of the PWR_ON/OFF pin is programmable. If hard wired in its active state the SMS66 will automatically initiate the Power-on sequence. Otherwise, toggling the PWR_ON/OFF pin to its active state will initiate the Power-on sequence. To enable software control of the sequencing feature, the SMS66 offers an I2C command to initiate Power-on sequencing while the PWR_ON/OFF pin is in its inactive state.
Figure 4D: SMS66 Sequence-On Waveforms Time/Horizontal division = 40mS
Ch 1(500mV/Div) = 3.3V DC-DC converter output (Yellow trace) Ch 2 (500mV/Div) = 2.5V DC-DC converter output (Blue trace) Ch 3 (500mV/Div) = 1.8V DC-DC converter output (Purple trace) Ch 4 (500mV/Div) = 1.5V DC-DC converter output (Green trace)
Figure 4E SMS66 Sequence-Off Waveforms Time/Horizontal division = 400mS
Ch 1(500mV/Div) = 3.3V DC-DC converter output (Yellow trace) Ch 2 (500mV/Div) = 2.5V DC-DC converter output (Blue trace) Ch 3 (500mV/Div) = 1.8V DC-DC converter output (Purple trace) Ch 4 (500mV/Div) = 1.5V DC-DC converter output (Green trace)
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SMS66
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
The SMS66 can be programmed to wait until either or both VDD and 12VIN inputs are within their respective voltage threshold limits before Power-on sequencing is allowed to begin. This ensures that the converters have their full supply voltage before they are enabled. Once Power-on sequencing begins, the SMS66 will wait a Power-on delay time (tDPON) for any channel in the first sequence position (0) and then activate the PUPX outputs for those channels. The Power-on delay times are individually programmable for each channel. The SMS66 will then wait until all VMX inputs of the channels assigned to the first sequence position (0) are above their programmed UV1 thresholds. At this point, the SMS66 will enter the second sequence position (1) and begin to timeout the Power-on delay times for the associated channels. This process continues until all of channels in the sequence have turned on and are above their UV1 threshold. The status registers indicates that all sequenced power supply channels have turned on. The programmable sequence termination timer can be used to protect against a stalled Power-on sequence. This timer resets itself at the beginning of each sequence position. All channels in the sequence position must go above their UV1 threshold before the sequence termination timer times out (tSTT) or the sequence will terminate and all PUPX outputs will be switched to their inactive state. The status registers contain bits that indicate the sequence has been terminated and in which sequence position the timer timed out. This timer has four settings of OFF, 100ms, 200ms and 400ms. While the SMS66 is in the Power-on sequencing mode the RST output is held active and the HEALTHY output is held inactive regardless of trigger sources. The Power-off and Force Shutdown trigger options are also disabled while in this mode. Furthermore, the SMS66 will not respond to activity on the PWR_ON/OFF pin or to a Power-off I2C command during Power-on sequencing mode. MONITORING Once the Power-on sequence is complete and before a Power-off sequence has been initiated, the SMS66 continues to monitor all VMX inputs, the VDD and 12VIN inputs, and two temperature sensor inputs with a 10-bit ADC. Each of these inputs is sampled and converted by the ADC every 2ms. The ADC input has a range of 0V to four times the voltage on VREF_ADC for inputs VMA-F and the VDD input. The range is extended to 12 times VREF_ADC for the 12VIN input and is reduced to two times VREF_ADC for the AIN1 and AIN2 inputs. The SMS66 monitors internal temperature using the 10-bit ADC and the automonitor function. Two under temperature and two over temperature thresholds can be set, each with its own programmable trigger options and consecutive conversion before trigger counter. Resolution is 0.25 C per bit scaled over the range of -128 C to 127.75 C. The temperature value can also be acquired over the I2C bus as a 10-bit signed two's complement value. The SMS66 compares each resulting ADC conversion with two programmable 10-bit under-voltage limits (UV1, UV2) and two programmable 10-bit over-voltage limits (OV1, OV2) for the corresponding input. A consecutive conversion counter is used to provide filtering of the ADC inputs. Each limit can be programmed to require 1, 2, 4 or 6 consecutive out-oflimit conversions before it is said to be in fault. One inlimit conversion will remove the fault from the threshold limit. This provides digital filtering of the monitored inputs. The ADC inputs VMA-F can use additional filtering by connecting a capacitor from the corresponding CAPX pins to ground to form an analog RC filter (R=25k). The input is considered to be in a fault condition if any of its limit thresholds are in fault. Setting an OV threshold limit to full-scale (3FFHEX), or setting an UV threshold limit to 000HEX ensures that the limit can never be in fault. The status registers provide the real-time status of all monitored inputs. The voltage threshold limits for inputs VMA-F, VDD and 12VIN can be programmed to trigger the RST and HEALTHY outputs as well as a Force Shutdown and Power-off operation when exceeded. The threshold limits for the internal temperature sensor and the AIN1 and AIN2 inputs can be programmed to trigger the RST, HEALTHY, and FAULT outputs.
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SMS66
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
The HEALTHY and FAULT outputs of the SMS66 are active as long as the triggering limit remains in a fault condition. The RST output also remains active as long as the triggering limit remains in a fault condition; however, once the trigger source goes away the RST will remain active for a reset timeout period (tPRTO). POWER-OFF SEQUENCING The SMS66 can be programmed to perform Power-off sequencing in either the same order or reverse order of Power-on sequencing. Power-off sequencing is the same as power-on sequencing and can be initiated by the PWR_ON/OFF pin, via I2C control or triggered by a fault condition on any of the monitored inputs. Toggling the PWR_ON/OFF pin to its inactive state will initiate the Power-off sequence. To enable software control of the Power-off sequencing feature, the SMS66 offers an I2C command to initiate Power-off sequencing regardless of the state of the PWR_ON/OFF pin. Furthermore, Power-off sequencing can be initiated by a fault condition on a monitored input. Once Power-off sequencing begins, the SMS66 will wait a Power-off delay time (tDPOFF) for any channel in the last sequence position (reverse order) and then deactivate the PUP outputs for those channels. The Power-off delay times are individually programmable for each channel. The SMS66 will then wait until all VMX inputs of the channels assigned to that sequence position are below their programmed OFF thresholds. At this point, the SMS66 will decrement to the next sequence position and begin to timeout the Power-off delay times for the associated channels. This process continues until all of channels in the sequence have turned off and are below their OFF thresholds. The status register reveals that all sequenced channels have turned off. The Power-off sequencing mode ends when all sequenced supplies are below their OFF thresholds. The programmable sequence termination timer can be used to protect against a stalled Power-off sequence. This timer resets itself at the beginning of each sequence position. All channels in the sequence position must go below their OFF threshold before the sequence termination timer times out (tSTT) or the sequence will terminate and all PUP outputs will be switched to their inactive state. This timer has four settings of OFF, 100ms, 200ms and 400ms. The sequence termination timer can be disabled separately for Power-off sequencing. While the SMS66 is in the Power-off sequencing mode the RST output is held active and the HEALTHY output is held inactive regardless of trigger sources. The Force Shutdown trigger option is also disabled while in this mode. Furthermore, the SMS66 will not respond to activity on the PWR_ON/OFF pin or to a Power-on I2C command during Power-off sequencing mode. FORCE SHUTDOWN The Force Shutdown operation brings all PUPX outputs to their inactive state. This operation is used for an emergency shutdown when there is not enough time to sequence the supplies off. The Force Shutdown operation shuts off all sequenced channels and waits for the supply voltages to drop below their respective OFF thresholds. A Force Shutdown operation can be initiated by any one of four events. The first two methods for initiating a Force Shutdown are always enabled. Simply taking the FS pin to its active state will initiate a Force Shutdown operation and maintain it until the pin is brought to its inactive state. An I2C Force Shutdown command allows the Force Shutdown operation to be initiated via software control. This I2C Force Shutdown command sets a volatile register bit that triggers a Force Shutdown. This bit is cleared after all sequenced channels have dropped below their OFF voltage threshold. During Power-on and Power-off sequencing, the sequence termination timer can initiate a Force Shutdown operation. As described in the previous sections, the sequence termination timer triggers a Force Shutdown operation if it times out before the power supply voltages surpass their voltage thresholds. This Force Shutdown will remain active until all sequenced power supply channels have dropped below their OFF voltage threshold. While the SMS66 is in monitor mode, a programmed fault condition on any power supply channel or on the 12VIN or VDD inputs can trigger a Force Shutdown. A Force Shutdown resulting from this will remain active until all sequenced power supply channels have dropped below their OFF voltage threshold.
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SMS66
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
RESTART OF POWER-ON SEQUENCING Once a Force Shutdown or Power-off operation has completed, the SMS66 can restart the Power-on sequencing. The device can be programmed to automatically restart after a Force Shutdown provided the PWR_ON/OFF pin remains in the active state or the I2C Power-on command remains in the command register. If this option is not selected, the SMS66 requires toggling of the PWR_ON/OFF pin or toggling of the I2C commands by issuing a Power-off command and then reissuing the Power-on command in order to restart Power-on sequencing. In either scenario, the FS pin will prevent the SMS66 from restarting Poweron sequencing. In addition, the device can be programmed to check that VDD and the 12VIN are within their programmed voltage thresholds before restarting Power-on sequencing.
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SMS66
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Figure 5 - SMS66 Applications schematic.
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SMS66
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 is available from the website (www.summitmicro.com). The SMX3200 programming Dongle/cable directly between a PC's parallel port and application. The device is then configured via an intuitive graphical user interface drop-down menus. interfaces the target on-screen employing The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMS66 via the programming Dongle and cable. An example of the connection interface is shown in Figure 6. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application.
D1 Positive Supply VDD_CAP 1N4148
Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND
SMS66
MR SDA SCL
10 8 6 4 2
9 7 5 3 1
0.1 F
GND Common Ground
Figure 6- SMX3200 Programmer I2C serial bus connections to program the SMS66. Note that the MR pin does not need to be connected to pin 6 for programming purposes.
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2070 1.0 7/16/03
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SMS66
Preliminary Information
I2C PROGRAMMING INFORMATION
SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the MSB. During data transfers SDA must remain stable while SCL is high. Data is transferred in 8-bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data. The SCL high period (tHIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 4-bit device type identifier (slave address) and a 3-bit bus address. The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMS66. The device type identifier for the memory array is generally set to 1010BIN following the industry standard for a typical nonvolatile memory. There is an option to change the identifier to 1011BIN allowing it to be used on a bus that may be occupied by other memory devices. The configuration registers are grouped with the memory array and thus use 1010BIN or 1011BIN as the device type identifier. The command and status registers as well as the 10-bit ADC are accessible with the separate device type identifier of 1001BIN. The bus address bits A1 and A0 are programmed into the configuration registers. Bus address bit A[2] can be programmed as either 0 or biased by the A2 pin. The bus address accessed in the address byte of the serial data stream must match the setting in the SMS66 and on the A2 pin. Any access to the SMS66 on the I2C bus will temporarily halt the monitoring function. This is true not only during the monitor mode, but also during Power-on and Power-off sequencing when the device is monitoring the channels to determine if they have turned on or turned off. The SMS66 halts the monitor function from when it acknowledges the address byte until a valid stop is received. WRITE Writing to the memory or a configuration register is illustrated in Figures 8, 9, 11, 13 and 14. A Start condition followed by the address byte is provided by the host; the SMS66 responds with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMS66 responds with an acknowledge; the host then clocks in on byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the configuration registers, memory, command and status registers and ADC registers must be set before data can be read from the SMS66. This is accomplished by a issuing a dummy write command, which is simply a write command that is not followed by a Stop condition. The dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device. The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figures 10, 12 and 15 for an illustration of the read sequence. WRITE PROTECTION The SMS66 powers up into a write protected mode. Writing a code to the volatile write protection register can disable the write protection. The write protection register is located at address 87HEX of slave address 1001BIN. Writing 0101BIN to bits [7:4] of the write protection register allow writes to the general-purpose memory while writing 0101BIN to bits [3:0] allow writes to the configuration registers. The write protection can re-
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SMS66
Preliminary Information enable by writing other codes (not 0101BIN) to the write protection register. Writing to the write protection register is shown in Figure 7. CONFIGURATION REGISTERS The majority of the configuration registers are grouped with the general-purpose memory located at either slave address 1010BIN or 1011BIN. The bus address bits, A[1:0], used to differentiate the general-purpose memory from the configuration registers are set to 11BIN. Bus address bit A[2] can be programmed as either 0 or biased by the A2 pin. Two additional configuration registers are located at addresses 83HEX and 84HEX of slave address 1001BIN. Writing and reading the configuration registers is shown in Figures 8, 9, 10,11 and 12. GENERAL-PURPOSE MEMORY The 4k-bit general-purpose memory is located at either slave address 1010BIN or 1011BIN. The bus address bits, A[1:0], used to differentiate the generalpurpose memory from the configuration registers are set to 00BIN for the first 2k-bits and 01BIN for the second 2k-bits. Bus address bit A[2] can be programmed as either 0 or biased by the A2 pin. The word address must be set each time the memory is accessed. Memory writes and reads are shown in Figures 13, 14 and 15. COMMAND AND STATUS REGISTERS The command and status registers are located at slave address 1001BIN. Writes and reads of the command and status registers are shown in Figures 16 and 17. ADC CONVERSIONS An ADC conversion on any monitored channel can be performed and read over the I2C bus using the ADC read command. The ADC read command, shown in Figure 18, starts with a dummy write to the 1001BIN slave address. Bits [6:3] of the word address byte are used to address the desired monitored input. Once the device acknowledges the channel address, it begins the ADC conversion of the addressed input. This conversion requires 70s to complete. During this conversion time, acknowledge polling can be used. The SMS66 will not acknowledge the address bytes until the conversion is complete. When the conversion has completed, the SMS66 will acknowledge the address byte and return the 10-bit conversion along with the 4-bit channel address echo. GRAPHICAL USER INTERFACE (GUI) Device configuration utilizing the Windows based SMS66 graphical user interface (GUI) is highly recommended. The software is available from the Summit website (www.summitmicro.com). Using the GUI in conjunction with this datasheet and Application Note 33, simplifies the process of device prototyping and the interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMS66. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I2C bus protocol.
Slave Address
Bus Address
Register Type Write Protection Register, Command and Status Registers, Two Configuration Registers, ADC Conversion Readout 1st 2-k Bits of General-Purpose Memory 2nd 2-k Bits of General-Purpose Memory Configuration Registers
1001BIN
A2 A1 A0
1010BIN or 1011BIN
A2 0 0 A2 0 1 A2 1 1
Table 1 - Address bytes used by the SMS66.
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SMS66
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
M aster
S T A R T 1 0 0 1
Bus Address A 2 A 1 A 0
Configuration Register Address = 87 HEX
Data = 55 HEX
S T O P 1 0 1 A C K
W A C K
1
0
0
0
0
1
1
1 A C K
0
1
0
1
0
Slave
8 H EX W rite Protection Register Address
7 HEX
5 HEX Unlocks General Purpose EE
5 HEX Unlocks Configuration Registers
Figure 7 - Write Protection Register Write
S T A R T 1 Slave 0 1 S A 0 S T O P D 2 D 1 D 0 A C K
Master
Bus Address A 2 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3
1
1
Figure 8 - Configuration Register Byte Write
S T A R T 1 Slave 0 1 S A 0
Master
Bus Address A 2 C 7 A C K C 6
Configuration Register Address C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0 A C K
1
1
W
Master D 7 Slave D 6 D 5
Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5
Data (16) D 4 D 3 D 2 D 1 D 0 A C K
S T O P
Figure 9 - Configuration Register Page Write
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SMS66
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S T A R T 1 Slave 0 1 S A 0 S T A R T C 1 C 0 A C K 1 0 1 S A 0
Master
Bus Address A 2 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2
Bus Address A 2
1
1
1
1
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0
A C K D 7 D 6 D 5 D 2 D 1 D 0
A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 10 - Configuration Register Read
S T A R T 1 Slave 0 0 1
Master
Bus Address A 2 A 1 A 0 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3 D 2 D 1 D 0 A C K
S T O P
Figure 11 - Configuration Register with Slave Address 1001BIN Write
S T A R T 1 Slave 0 0 1 S T A R T C 1 C 0 A C K 1 0 0 1
Master
Bus Address A 2 A 1 A 0 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2
Bus Address A 2 A 1 A 0
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0
A C K D 7 D 6 D 5 D 2 D 1 D 0
A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 12 - Configuration Register with Slave Address 1001BIN Read
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SMS66
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S T A R T 1 Slave 0 1 S A 0 S T O P D 2 D 1 D 0 A C K
Master
Bus Address A 2 0 / 1 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3
0
Figure 13 - General Purpose Memory Byte Write
S T A R T 1 Slave 0 1 S A 0
Master
Bus Address A 2 0 / 1 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0 A C K
0
Master D 7 Slave D 6 D 5
Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5
Data (16) D 4 D 3 D 2 D 1 D 0 A C K
S T O P
Figure 14 - General Purpose Memory Page Write
S T A R T 1 Slave 0 1 S A 0 S T A R T C 1 C 0 A C K 1 0 1 S A 0
Master
Bus Address A 2 0 / 1 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2
Bus Address A 2 0 / 1
0
0
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0
A C K D 7 D 6 D 5 D 2 D 1 D 0
A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 15 - General Purpose Memory Read
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SMS66
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S T A R T 1 Slave 0 0 1 S T O P D 2 D 1 D 0 A C K
Master
Bus Address A 2 A 1 A 0 C 7 A C K C 6
Command and Status Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3
Figure 16 - Command and Status Register Write
S T A R T 1 Slave 0 0 1 S T A R T C 1 C 0 A C K 1 0 0 1
Master
Bus Address A 2 A 1 A 0 C 7 A C K C 6
Command and Status Register Address W C 5 C 4 C 3 C 2
Bus Address A 2 A 1 A 0
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0
A C K D 7 D 6 D 5 D 2 D 1 D 0
A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 17 - Command and Status Register Read
S T A R T 1 Slave 0 0 1 S T A R T 0 0 0 A C K 1 0 0 1
Master
Bus Address A 2 A 1 A 0
Channel Address C H 3 C H 2 C H 1 C H 0
Bus Address A 2 A 1 A 0
W A C K
0
R N A C K
Master
S T A R T 1 0 0 1
Bus Address A 2 A 1 A 0
Channel Address Echo C H 3 C H 2 C H 1 C H 0 D 9 D 8
A C K 0 D 7
10-Bit ADC Data D 6 D 5 D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
R A C K
0
Slave
Figure 18 - ADC Conversion Read
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SMS66
Preliminary Information
DEFAULT CONFIGURATION REGISTER SETTINGS - SMS66-171
Register R0C R0D R0E R0F R10 R11 R12 R13 R14 R15 R18 R19 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R3A R3B R3C R3D R3E R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R4A
RC1
Contents 00 00 03 A1 8F 9F AF BF CF DF 00 00 0D 60 0D DC 0E 45 0E A2 0F 08 0F D6 00 12 48 0D B9 0E 39 0E A4 0F 16 0F B4 06
Register R4B R4C R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R8A R8B R8C R8D R8E R8F R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R9A R9B R9C R9D R9E R9F RA0 RA1 RA2 RA3
Contents 7F 00 42 48 82 3E 2A B8 12 F6 41 C8 81 B9 2A 34 12 49 49 5C 81 52 29 D7 11 EB 41 3E 81 33 29 9A 11 AE 41 0B 80 F6
Register RA4 RA5 RA6 RA7 RA8 RA9 RAA RAB RAC RAD RAE RAF RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RBA RBB RBC RBD RBE RBF RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9
Contents 29 5D 11 71 40 CE 80 8F 29 1F 11 33 2A 67 0A 52 03 FF 03 FF 0D 9A 0D 56 0F E0 0F E0 0B 38 0B 38 09 90 09 90 0C 00
Register RCA RCB RCC RCD RCE RCF RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 REA REB R83 R84
Contents 0C 00 0F FF 0F FF 0C 00 0C 00 0F D8 0F D8 00 3D 00 3D 00 3D 00 3D 00 3D 00 3D 05 00
The default device ordering number is SMS66F-171, is programmed as described above and tested over the commercial temperature range. Application Note 42 contains a complete description of the Windows GUI and the default settings of each of the 142 individual Configuration Registers.
Summit Microelectronics, Inc
2070 1.0 7/16/03
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SMS66
Preliminary Information
PACKAGE
48 PIN TQ FP PACKAGE
0.354 (9.00) 0.276 (7.00) BSC (A) BSC (B) Inches (Millimeters)
0.02 (0.5)
BSC
0.007 - 0.011 (0.17 - 0.27)
DETAIL "A"
(B) (A)
Ref Jedec M S-026
0.037 - 0.041 0.95 - 1.05 Pin 1 Indicator 0.039 (1.00)
Ref
0.047 MAX. (1.2)
0 o Min to 7 o Max
A
B
0.002 - 0.006 (0.05-0.15)
0.018 - 0.030 (0.45 - 0.75)
DETAIL "B"
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SMS66
Preliminary Information
PART MARKING
SUM M IT SM S66F Annn
Pin 1
Summit Part Number
xx
Status Tracking Code (Blank, MS, ES, 01, 02,...) (Sum m it Use)
AYYW W
Date Code (YYW W )
Lot tracking code (Sum m it use) Part Num ber suffix (Contains Custom er specific ordering requirem ents)
Drawing not to scale
Product Tracking Code (Sum m it use)
ORDERING INFORMATION
SMS66 Summit Part Number F nnn Part Number Suffix (see page 24) Package F=48 Lead TQFP
NOTICE
NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 1.0 - This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at
Specific requirements are contained in the suffix such as Commercial or Industrial Temp Range, Hex code, Hex code revision, etc.
www.summitmicro.com for data sheet updates.
(c) Copyright 2003 SUMMIT MICROELECTRONICS, Inc. I2C is a trademark of Philips Corporation.
Power Management for CommunicationsTM
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